Continuously reducing the size of solid-state memory architecture is an effective way to increase the capacity of such memories for a given amount of circuit real estate. However, the resulting feature size can give rise to design and process challenges. One of these challenges relates to an unwanted parasitic voltage drop that occurs at the location of a selected cell. In particular, when a selection voltage(s) (e.g., Vsel or 0 V) for an associated memory operation is applied from one or more relevant drivers to a corresponding one of a selected access line (e.g., WL) and a selected sense line (e.g., BL) associated with the selected cell, the actual voltage across the selected cell (e.g., Vcell) may become lower than difference between the applied selection voltage(s) (Vsel−0 V=Vsel). Such an unwanted voltage (IR: current*resistance) drop at the selected cell may occur due to parasitic current leakage. Sometimes, the voltage drop caused by the parasitic current leakage may corrupt the outcome of a memory operation.